1. Field of the Invention
The invention relates to magnetic recording of data and more particularly to pre-compensation in writing of data to a magnetic medium.
2. Description of the Related Art
In magnetic recording, data is written on or read from one or more data tracks of a magnetic storage medium such as a hard disk. The data tracks generally form concentric rings on the surfaces of each of plural hard disks that constitute the magnetic recording device. When writing to such a track, the disk is rotated at predetermined speed, and electrical signals applied to a magnetic read/write head floating over the track are converted to magnetic transitions on the track. The magnetic transitions represent digital data encoded so that each transition may correspond to a ONE bit value and the absence of a transition may correspond to a ZERO bit value as in a xe2x80x9cnon return to zero invertedxe2x80x9d (NRZI) encoding.
To obtain high density recording, magnetic transitions representing data patterns are closely packed on the hard disk magnetic medium. Each transition or absence of a transition of the recording bit sequence is located in a window in which a flux reversal may occur. Such closely packed data bits influence each other so that non-linear magnetic shifting of transitions and bit interference are likely to occur during recording. As a result, the reading of the high density recorded data pattern may be adversely affected. In an example, any device mismatch in a high data rate write data path causes positive/negative transition skew known as pulse pairing so that writing of a single tone square wave can result in a write transition spacing that has other than a 50% duty cycle.
When writing to a high density magnetic recording channel, it is therefore necessary to adjust the position of transitions in the data stream to correct for the influence of nearby transitions so that transitions in the recovered data stream are evenly placed. Such precompensation of data being recorded is accomplished by changing the timing of the magnetic flux reversal in a clock period to offset the magnetic transition shift and interference effects of adjacent and nearby bits. In this way, the transition shift of a bit due to the pattern of preceding and/or succeeding bits is anticipated and the bit recording time is changed to compensate for the magnetic transition shift due to the effects of surrounding bits.
In one type of known precompensation exemplified by the disclosure of U.S. Pat. No. 4,878,028 issued to Y. C. Wang Oct. 31, 1989, a precompensation delay arrangement for writing data to disks has plural delay information elements, each providing a fixed delay that is a percentage of the bit cell time period according to the data bit pattern. In the recording of the data pattern, one of the delay information elements is selected to provide a preset delay (early, nominal, or late) for recording a present data bit according to the preceding data bit pattern.
In another type of precompensation exemplified by U.S. Pat. No. 6,133,861 issued Oct. 17, 2000 to G. Jusuf et al. and assigned to the same assignee, each of multiple decoders is supplied with a selectably variable version of a master clock. The delayed versions of the master clock are stably produced by delay elements using delay-locked feedback loops. Each of the delay elements is set at a different fixed delay and provides a differently delayed clock signal to a decoding circuit to which data to be recorded is supplied. A selection circuit selects one of the data decoding circuits responsive to the pattern of the preceding data bits.
In the aforementioned and other prior art arrangements, the timing of recording of each data bit is shifted to precompensate for the preceding data bit pattern. It is, however, required to provide 2N delay altering elements each having a different delay to provide precompensation for a data pattern of N data bits. Accordingly, while only 4 delay altering elements generating different delays are needed for precompensation of a 2 data bit pattern, the number of required delay defining elements increases as the data bit pattern is increased. Eight delay altering elements are needed for precompensation based on a three data bit pattern and 16 delay altering elements are needed for precompensation based on a 4 data bit pattern. The increased number of delay altering elements to precompensate for larger data bit patterns adds to the cost and the complexity of magnetic recording system. Accordingly, It is desirable to provide a precompensation arrangement which utilizes a predetermined number of delay elements which is independent of the size of data bit patterns used for precompensation.
The invention is directed to a precompensation arrangement for magnetic recording of data signals in which a clock generator generates clock signals at a predetermined rate to clock the data signals to be recorded. Plural clock delay units provide delays to control the recording times of the data signals according to patterns of adjacent data signals. Recording of each data signal is delayed on the basis of the states of the adjacent data signals.
According to the invention, a clock delay generator generates clock delay data relative to the generated clock signals for each successive data signal responsive to the pattern of adjacent data signals. n greater than 1 clock delay units operate to control recording times of the successive data signals according to the clock delay data. Each clock data unit generates an output signal that determines the recording time of one data signal in each sequence of n successive data signals according to the clock delay data received by the clock data unit for that data signal.
According to one aspect of the invention, one clock delay unit receives the clock delay data corresponding to an mth data signal while the clock delay unit that received the clock delay data corresponding to the (mxe2x88x92n+1)th data signal generates the output signal to determine the recording time of the (mxe2x88x92n+1) data signal.
According to another aspect of the invention, each clock delay unit is a reprogrammable clock delay unit that is reprogrammed according to the clock delay data for the one data signal received in each sequence of n data signals.
According to another aspect of the invention, each pattern of adjacent data signals includes one set of data signals immediately preceding the data signal for which clock delay data is generated, a set of data signals immediately succeeding the data signal for which the clock delay data is generated or a set of data signals surrounding the data signal for which the clock delay data is generated.
According to yet another aspect of the invention, a selector sequentially selects the output signals of the n clock delay units in each n data signal sequence to control the recording times of the successive data signals of the sequence.
According to yet another aspect of the invention, the clock delay generator includes a look up table which forms clock delay information relative to the generated clock signal for each successive data signal according to the pattern of adjacent data signals for each successive data signal.
According to yet another aspect of the invention, a reference clock delay unit produces reference clock delay data corresponding to the predetermined clock rate in response to the generated clock signals.
According to yet another aspect of the invention, the clock delay generator includes a look up table that produces clock delay information according to the set of adjacent data signals for each data signal, a unit that produces a reference clock delay signal and a unit that combines the clock delay information and the reference clock delay signal to form the clock delay data for each data signal.
According to yet another aspect of the invention, the reference clock delay unit includes a reprogrammable clock delay unit that is reprogrammed according to changes in the predetermined clock rate.
According to yet another aspect of the invention, a calibration unit calibrates each of the n clock delay units to the changed predetermined clock rate in response to a change in the predetermined clock rate.
According to yet another aspect of the invention, the calibration unit includes a comparator that compares the output signal of the reference clock delay unit to the output signals of the n clock delay units to form a reference value for each of the n clock delay units.
According to yet another aspect of the invention, each clock unit includes an interpolator for interpolating received clock delay data.
According to yet another aspect of the invention, each clock delay unit includes a phase locked loop that generates a data signal determining output in response to the clock delay data from the clock delay generator.
In an embodiment illustrative of the invention, the timing of data signals to be magnetically recorded is controlled by a precompensation circuit that includes a clock delay generator having a look up table to generate clock delay data for each successive data signal according to the pattern of adjacent data signals surrounding the data signal, a set of n same type programmable phase locked loop delay units operating sequentially to control the recording times of successive data signals based on the clock delay data and a calibrator that calibrates the programmable phase locked loop delay units to accommodate changes in recording clock rate. During writing of the data signals, each phase locked loop delay unit receives clock delay data for a one data signal in each sequence of n successive data signals and generates a delay output signal that sets the recording time of that data signal. While one phase locked loop delay unit receives the clock delay data for the mth data signal, the phase locked loop delay unit that received the (mxe2x88x92n+1)th data signal in the sequence outputs a signal to time the recording of the (mxe2x88x92n+1)th data signal. In response to a change in clock rate, the clock delay data for each delay unit is calibrated for the changed clock rate using a reference phase locked loop delay unit set according to the clock rate.